J-core is a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license.
The SuperH processor is a Japanese design developed by Hitachi in the late 1990's. As a second generation hybrid RISC design it was easier for compilers to generate good code for than earlier RISC chips, and it recaptured much of the code density of earlier CISC designs by using fixed length 16 bit instructions (with 32 bit register size and address space), using microcoding to allow some instructions to perform multiple clock cycles of work. (Earlier pure risc designs used one instruction per clock cycle even when that served no purpose but to make the code bigger and exhaust the encoding space.)
Hitachi developed 4 generations of SuperH. SH2 made it to the United states in the Sega Saturn game console, and SH4 powered the Sega Dreamcast. They were also widely used in areas outside the US cosumer market, such as the japanese automative industry.
The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.
The LoongArch architecture is an Instruction Set Architecture (ISA) that has Reduced Instruction Set Computer (RISC) style. The LoongArch Reference Manual is used to explain the LoongArch specification.
LoongArch has the typical characteristics of RISC. LoongArch instructions are of fixed size and have regular instruction formats. Most of the instructions have two source operands and one destination operand. LoongArch is a load-store architecture; this means only the load/store instructions can access memory the operands of the other instructions are within the processor core or the immediate number in the instruction opcode.
LoongArch is divided into two versions, the 32-bit version (LA32) and the 64-bit version (LA64). LA64 applications are “application-level backward binary compatibility” with LA32 applications. That means LA32 applications can run directly on the machine compatible with LA64, but the behavior of system softwares (such as the kernel) on the machine compatible with LA32 is not guaranteed to be the same as on the machine compatible with LA64.
LoongArch is composed of a basic part (Loongson Base) and an expanded part, as shown in the figure. The expansion part includes Loongson Binary Translation (LBT), Loongson VirtualiZation (LVZ), Loongson SIMD EXtension (LSX), and Loongson Advanced SIMD EXtension(LASX).
License: CC BY-NC-ND v4.0 International
lowRISC is an open source RISC-based system-on-a-chip and accompanying development board. Based on the 64-bit RISC-V instruction set and architecture. Designed to be a fully open source and very low cost general purpose computer.
The J2 is a clean-room designed FOSS processor core and SOC that implements the SuperH instruction set. hardware VHDL BSD license. Royalty and patent free. Compile the VHDL into a bitstream and upload it into an FPGA. Known to run Linux. Hybrid RISC architecture, fixed-length 16-bit instructions, 32-bi registers and address space. Has no MMU for now but it's in the works due to patent issues. Cheap to manufacture (roughly $0.03/processor). security audited.
A company that sells opensource RISC processor cores. Linux compatible. RISC-V in particular. 32-bit and 64-bit. Prides itself on having no NDAs, all datasheets are available for download. Embedded cores, too. Free access to FPGA bitstreams for testing, benchmarking, and development.