lowRISC is an open source RISC-based system-on-a-chip and accompanying development board. Based on the 64-bit RISC-V instruction set and architecture. Designed to be a fully open source and very low cost general purpose computer.
The J2 is a clean-room designed FOSS processor core and SOC that implements the SuperH instruction set. hardware VHDL BSD license. Royalty and patent free. Compile the VHDL into a bitstream and upload it into an FPGA. Known to run Linux. Hybrid RISC architecture, fixed-length 16-bit instructions, 32-bi registers and address space. Has no MMU for now but it's in the works due to patent issues. Cheap to manufacture (roughly $0.03/processor). security audited.
A company that sells opensource RISC processor cores. Linux compatible. RISC-V in particular. 32-bit and 64-bit. Prides itself on having no NDAs, all datasheets are available for download. Embedded cores, too. Free access to FPGA bitstreams for testing, benchmarking, and development.
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