J-core is a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license.

The SuperH processor is a Japanese design developed by Hitachi in the late 1990's. As a second generation hybrid RISC design it was easier for compilers to generate good code for than earlier RISC chips, and it recaptured much of the code density of earlier CISC designs by using fixed length 16 bit instructions (with 32 bit register size and address space), using microcoding to allow some instructions to perform multiple clock cycles of work. (Earlier pure risc designs used one instruction per clock cycle even when that served no purpose but to make the code bigger and exhaust the encoding space.)

Hitachi developed 4 generations of SuperH. SH2 made it to the United states in the Sega Saturn game console, and SH4 powered the Sega Dreamcast. They were also widely used in areas outside the US cosumer market, such as the japanese automative industry.

The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.

An FPGA powered hardware platform for emulating the MOS 6581 and 8580 SID chips. It is a fully functional device that can be installed into a Commodore computer as a pin-compatible replacement.

Vortex is a full-stack open-source RISC-V GPGPU. Support RISC-V RV32IMAF and RV64IMAFD. Configurable number of cores, warps, and threads. Configurable number of ALU, FPU, LSU, and SFU units per core. Configurable pipeline issue width. Optional local memory, L1, L2, and L3 caches. OpenCL 1.2 Support.

Supported FPGAs: Altera Arria 10 and Stratix 10, Xilinx Alveo U50, U250, U280, Xilinx Versal VCK5000.

James Bowman's seminal paper on the J1 CPU was presented in 2010. At under 200 lines of Verilog, the J1 was a real breakthrough in simplicity. It also happens to be a very powerful Forth processor.

The Chad CPU, like the J1, has excellent semantic density. The application of the J1 was a UDP stack in a Xilinx FPGA. The code was 70% smaller than the equivalent C on a MicroBlaze. The code just wouldn't fit in memory, so the J1 was used instead. Admittedly, MicroBlaze is a hog. However J1 has a lot going for it. Calls and jumps take only a single cycle. Often a return is combined with an ALU instruction to cause a return in zero instructions. It's a little freaky to watch in simulation if you're used to control flow changes having to deal with pipelines.

The system can be understood and maintained by one person due to simplicity.

Built for security. The ISA doesn't support random read of code memory, which makes reverse engineering and hacking the code an exercise in chip probing if it can even be done. The MCU boots from SPI flash, which is encrypted using a stream cipher. The weak spot then becomes key management: How secure are keys, how hard can you make it to probe memory busses on the ASIC die, etc.

In-system programming (ISP) is handled by hardware state machines, not firmware. The SPI flash controller integrates a UART and processor memories so that the RAMs can be loaded from flash at boot time. The UART can also be used to program flash by any host computer with a serial port. It can also reset the processor.

Glasgow is a tool for exploring digital interfaces, aimed at embedded developers, reverse engineers, digital archivists, electronics hobbyists, and everyone else who wants to communicate to a wide selection of digital devices with high reliability and minimum hassle. It can be attached to most devices without additional active or passive components, and includes extensive protection from unexpected conditions and operator error.

Nyuzi is an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like deep learning and image processing.

This project includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

An overview of the OpenRISC architecture and how to get started using it. Briefly talks about synthesizing an FPGA bitstream, setting up a development environment, and either emulating it or running it inside an FPGA. Also covers cross compiling an OS for it.

The J2 is a clean-room designed FOSS processor core and SOC that implements the SuperH instruction set. hardware VHDL BSD license. Royalty and patent free. Compile the VHDL into a bitstream and upload it into an FPGA. Known to run Linux. Hybrid RISC architecture, fixed-length 16-bit instructions, 32-bi registers and address space. Has no MMU for now but it's in the works due to patent issues. Cheap to manufacture (roughly $0.03/processor). security audited.

A company that sells opensource RISC processor cores. Linux compatible. RISC-V in particular. 32-bit and 64-bit. Prides itself on having no NDAs, all datasheets are available for download. Embedded cores, too. Free access to FPGA bitstreams for testing, benchmarking, and development.